Bart Bergman
12190 168th Street West
Lakeville, Minnesota 55044
Cellular: 952-250-2887
E-mail: bbergman@arrowsmith-research.com

I am an expert in both semiconductor development and in the EDA software tools used to design them. This expertise exists in both the technical and business domains. I have been a trailblazer in new technologies and methodologies in technology nodes from 1.5 micron down to 65 nm. My technical experience and perspective comes from my experiences as a silicon designer, an EDA developer, an application engineer, a consultant and as a software architect/manager. My silicon designs have successfully taped out and been put into production in computer systems, networking equipment, graphics processors and generic ASIC’s.  My business skills were developed by marketing and selling EDA tools, design services and both large and small silicon IP.  My business skills have been validated by my ability to achieve aggressive goals. I have always delivered financial results well above quota and often have been the sole source of funds for startups. These interdisciplinary skills utilized across a range of electronics industries and markets lead to broad situational fluency. I am a businessman who negotiates balanced agreements and a technologist who is very adept at working with leading edge tools and technologies.
 

RECENT CAREER HISTORY AND RESULTS
PRESIDENT AND FOUNDER Arrowsmith Research Company
Assignments

Developed a production flow for Statistical STA using EinStat at ATI

Methodology lead for Statistical Static Timing of Processor cores at LSI (Characterization-Hspice, Physical Synthesis-ICC, Extraction-STAR-RCXT and SSTA-PT-VX)

Tool developer/Architect/Designer for LSI's RapidChip tools
Timing lead for the first 65 nm IBM SerDes testchip

Senior Physical Implementation/Timing Engineer for Cisco ASIC

ASIC lead for the first LSI Rapidchip design

Tool developer/Architect for Arrowsmith Research's EDA tools

Tools and technologies

Four years experience in 65 nm CMOS technologies (IBM and TSMC foundries)

Seven years experience in Physical synthesis(ICC-Synopsys, Chipbench-IBM Blastfusion- Magma, Synplify ASIC-Synplicity)

Four years of STA and extensive experience with SSTA gained through using IBM(EinStat), Synopsys(PT-VX) and Magma(QuartzTime)

Additional technical expertise throughout a Timing Methodology flow including Timing Characterization and Parasitic Extraction

Executive experience in Sales, Marketing, and Management